As a result of the increasing miniaturization of electronic components generally and memory products in particular, it is becoming more and more important to complete the transition from planar to vertical structures in order to achieve larger packing densities in conjunction with geometries that are still manageable in terms of fabrication technology. In the case of NROM memories, it is conceivable to embody the oxide-nitride-oxide layer (ONO) with a U-shaped cross section (UMEM component), so that a larger channel length does not necessarily take up a larger chip area. In this case, the individual memory cells are formed as transistor structures in a trench in the semiconductor material. In the case of the transistor structures, an oxide-nitride-oxide layer sequence is present as storage medium in each case between a source region and the gate electrode and between a drain region and the gate electrode. Such a configuration of the memory cells is described in DE 100 39 441 A1.